Such an arrangement is already known in the art, e.g. from the published International Patent Application PCT/AU85/00304. Therein the communication channel comprises two oppositely directed unidirectional busses to both of which the units are connected. The latter units each include two queues of data packets to be transmitted over a respective bus: e.g. packets of a first queue are transmitted over a first bus and packets of a second queue are transmitted over a second bus. The latter packets include the access request word and a busy field. When upon receipt of the access request word, e.g. on the first bus, a unit wants to transmit a packet of the second queue, it registers its own priority in the request word by marking the assigned channel thereof provided that this channel is free. If not, the unit waits for the next access request word. Each unit includes a counter which is incremented by one for each priority, marked in the passing access request words and which is higher than its own priority. The counter is decremented by one for each data packet passing on the second bus and having a not activated busy field, i.e. the data packet is empty. When the latter counter has a zero value at the moment an empty packet passes on the second bus, the unit may access the bus and use the latter packet to store data in it. In this way access to the communication channel by a unit is inhibited as long as the data packets passing by are not empty and as long as the latter unit's counter has not reached the zero value.
Due to the presence of the dual bus and the counters, the known access control arrangement is of a rather complicated structure.